VistaBuzz – Latest News, Entertainment, Viral Videos And More

Delivers the most interesting trending materials that are going on the internet including and not limited to, news, entertainment, viral videos, and more…

Saturday August 15, 2020

Intel unveils new transistor technology and showcases its latest innovations at the Engineering Architecture Day 2020 event

During a press conference held by Intel on the occasion of Engineering Architecture Day 2020, Raja Kodori, the company’s chief architecture engineer, and a number of fellow engineers highlighted the progress Intel has made in its six pillars of technical innovation.

Intel has unveiled SuperFin 10nm technology, which represents the largest internal processor development in the company’s history, and with it it provides significant performance improvements comparable to the entire processor switching process.

Intel has also unveiled the details of Willow Cove and Tiger Lake architecture for its customers in the mobile sector, as well as providing a first glimpse of the architecture of Xe graphics processors, which enables its services in different markets ranging from consumer applications to high-performance computing to gaming uses.

Intel says it is developing a pioneering range of products within its broad portfolio to offer to customers thanks to its detailed design-based approach, advanced packaging technology, XPU processor offerings and its software-based strategy.

Here are the technologies Intel talked about:

In the following points, we review the technologies that Intel has developed and is preparing to launch them in the market, according to the press release: It includes SuperFin 10nm technology, encapsulation, Willow Cove and Tiger Lake core architecture, hybrid architecture, Xe engineering architecture, and data center architecture.

SuperFin 10nm technology

  • After many years of efforts to optimize the FinFET transistor, Intel is redeveloping this pioneering technology to achieve the largest internal processor development in its history, providing a performance improvement that matches the entire processor switching process. Technology is incorporated SuperFin 10 nm Intel Optimized FinFET transistors with metal-insulator-metal design capacitor. Super VPN provides advanced source / drain layer pattern, enhanced gateway operations, and an additional gateway point to boost performance levels by:
      • Improving the stratification of crystal structures at the source and drain level, thus increasing the voltage and reducing the resistance to pass more electrical current into the processor channel.
      • Optimized gate process to enhance transmission levels across channels, which speeds up the movement of electric charge carriers
      • Provides the option to activate an additional gate to pass a greater electrical current when specific jobs require extreme levels of performance
      • The use of a thin shield to reduce the current resistance by 30% and improve the interconnection performance
      • Achieving a 5-fold increase in capacity in the same area when compared with industry standards, resulting in reduced voltage drop levels, and thus significantly improved product performance. This technology is available thanks to the provision of a new class of Hi-K dielectric materials, which are stacked in very thin layers with a thickness of several angstroms (1 angstroms = 0.1 nanometers) to form an ultra-fine mesh structure. This technology is the first of its kind in the sector and far surpasses the current capabilities of other manufacturers.
  • The next generation mobile processors, known as Tiger Lake, are based on 10nm SuperFin technology. These processors are currently being manufactured and are expected to be shipped to customers with OEM systems during the upcoming holiday season.

Encapsulation

  • Was registered Hybrid bonding test wizard During the second quarter of 2020. The hybrid bonding technology is an alternative to the thermal stress bonding currently used in most packaging technologies, and enables contact points as small as 10 microns or less, providing higher interconnection density and bandwidth at energy levels Less.

Engineering architectures for Willow Cove and Tiger Lake processors

  • form Willow Cove Next generation Intel® microprocessor architecture. Building on the latest developments in processes, SuperFin 10nm technology, and the foundation of Sunny Cove architecture, Willow Cove architecture improves CPU performance while providing significant improvements in frequency and power efficiency. It also enables a redesigned cache architecture to provide a larger capacity of 1.25MB MLCs, as well as improved security thanks to Intel’s CET enforcement technology.
  • Handlers will be provided Tiger Lake Smart performance with explosive development in the major trends of the computing sector. And through improvements that include the CPU, accelerators based on artificial intelligence, and being the first engineering architecture that adopts system technology on the chip with the Xe-LP microarchitecture for graphics processors; Tiger Lake architecture will provide a significant increase in CPU performance, a quantum leap in graphics performance with an integrated set of the best Internet protocols over system technology on a chip such as the embedded Thunderbolt 4 speed connection standards. The Tiger Lake architecture based on system technology on chip provides the following advantages :
    • New Willow Cove architecture CPU core – with dramatically increased frequency levels based on 10nm SuperFin technology.
    • New Xe GPU architecture with up to 96 EUs and significant performance improvements per watt.
    • Energy Management – Incorporating independent DVFS dynamic voltage tuning technology into a coherent architecture, increasing the efficiency of the fully integrated voltage regulator FIVR.
    • Architecture and Memory – Twice the bandwidth for Coherent Architecture, memory bandwidth of ~ 86 GB / s, compatible with LP4x-4267 and DDR4-3200; With an engineering build capacity of LP5-5400.
    • GNA 2.0 Gaussian Network Accelerator for Internet protocols to reduce the power consumption of neural computing processes from the CPU. 20% less Gaussian network accelerator vs. CPU usage (turn on workload noise reduction).
    • Process Information IO – Built-in TB4 / USB4 Ports, Integration of 4th Generation PCIe Fast Plug-In Port on CPU to reduce time lag, high-bandwidth device’s access to memory.
    • Display – simultaneous memory bandwidth of up to 64GB / s to power multiple high-resolution displays. A dedicated path in the architecture to memory to maintain QoS.
    • Intel Platform Update (IPU6) – Up to 6 sensors with 4K30 video port, 27MP photo, 4K90 and 42MP image engineering capacity.

Hybrid geometry

  • Intel is developing its hybrid architecture with the Alder Lake processor, the company’s second-generation consumer product. These processors will combine two prospective architectures, Golden Cove and Gracemont, to provide high levels of performance / power consumption.

Graphics processor Xe architecture

  • A detailed description of the microarchitecture was provided by Intel Xe-LP (Low Energy) and software designed specifically to enhance efficiency levels of mobile platforms. The Xe-LP is Intel’s most efficient architecture for desktop and laptop platforms, providing up to 96 execution units, and comes with new engineering designs that include asynchronous computing tasks, display clarification, sampler feedback, and an updated media engine with AV1 software. And an updated rendering engine. This will provide end users with a wide range of benefits that include instant game tuning, capture and broadcasting, and enhanced shooting accuracy. As for software development, the Xe-LP architecture will provide many improvements through the new path of DX11 software and an improved assembly tool.
  • The first slide has been played Xe-HP And tried it in the labs successfully. Xe-HP is the world’s first scalable, high-performance multi-panel architecture that delivers data center-like capabilities, unrivaled media performance, GPU scalability and AI optimization. It covers a computing dynamic range from 1 to 2 to 4 panels, and works like a multi-core GPU. During the Architecture Day events, Intel demonstrated the performance of Xe-HP architecture that included 10 broadcasts of 4K videos at 60 fps on a single board. Another demonstration showed the computing capability of the Xe-HP architecture on multiple boards. Intel is currently providing samples of Xe-HP architecture to its major customers and plans to enable their useBy the developers at DevCloud. The Xe-HP processor will be introduced next year.
  • Intel introduced a new microarchitecture inspired by the Xe architecture and bearing the name Xe-HPGCombining high performance with energy efficiency, it is designed to provide enhanced gaming experiences, and is inspired by Xe-LP architecture while leveraging Xe-HP architecture standards to provide greater configuration and computing frequency optimization based on Xe-HPC architecture. A new memory subsystem based on GDDR6 memory has been added to improve performance and price levels, and the Xe-HPG architecture will support ray tracing acceleration. Xe-HPG engineering is expected to start shipping in 2021.
  • Prepare Intel SG1 GPU The company’s first discrete Xe-based GPU for data centers. The SG1 processor is based on its performance on four DG1 processors as a small form factor used in data centers, as it is designed to reduce time lag and provide high density for Android games and video streaming. The SG1 processors will be shipped later this year and will be in production soon.
  • Intel Xe-based graphics processors entered – and bear the name processor DG1 – Production phase, and will start shipping during the year 2020. DG1 processors are currently available on Intel DevCloud devices, and are available to users with early access. The DG1 processor, unveiled at CES, is the first discrete graphics processor from Intel specifically designed for desktop computers and is based on the Xe-LP microarchitecture.
  • Intel Graphics Control Center is equipped with a host of new features including: Instant game tuning and game sharpening.
    1. The Online Tuning feature is a dedicated gaming program, and allows end users to be provided with fixes and improvements at an unprecedented speed without the need to download and install a full program; The user is required to register only one subscription per game.
    2. The game rendering feature uses Perceptual Adaptive Sharpness, which is an algorithm to adapt the display sharpness based on shadow computing that enhances image clarity in games. This feature is especially useful for use in games that adopt a resolution of display to balance performance and image quality, and it is available as a subscription feature through the Intel GPU.

Data center architectures

  • Prepare Ice Lake Intel’s first Xeon Scalable 10nm processor, due for release by the end of 2020, will provide high levels of performance in both productivity and workload levels. The new processor will provide a set of advanced technologies that include total memory encryption, the fourth generation of fast accessory port (PCIe), eight memory channels, as well as a set of improvements that speed up the encryption processes. A host of web storage and IoT editions will also be offered within the Ice Lake product range.
  • form Sapphire Rapids The next generation of Intel Xeon Scalable processors, based on enhanced SuperFin technology, will provide a wide range of industry-leading technologies including DDR5 memory, fifth-generation Rapid Accessory Port (PCIe), and Compute Express Link 1.1 capabilities. The Sapphire Rapids will take over the CPU of the Aurora Exascale supercomputer system at Argonne National Laboratory. The processor will continue Intel’s strategy for embedded AI acceleration solutions with a new acceleration system called Advanced Matrix Extensions. Initial deliveries of Sapphire Rapids are expected to start production during the second half of 2021.
  • Intel continues to innovate to develop and demonstrate FPGA technologies and third-generation groundbreaking transceivers with the first Next generation transmitter and receiver Worldwide out of the model 224G-PAM4 TX.

Software

  • Intel intends to launch an interface oneAPI Gold Later in the year to provide software developers with the highest levels of production quality and efficiency using unstructured, oriented, matrix, and spatial architectures. The company launched the eighth version of the oneAPI Beta interface last July, which provides a new set of benefits and improvements in the areas of distributed data analytics, performance enhancement, profiling, and the video and records library. And is available Discrete GPU DG1 For developers with early access via device DevCloud From Intel, Which gives them access to libraries and development tools to enable them to start programming operations using oneAPI before they have the necessary hardware.
  • These news and disclosures highlight the progress Intel has made towards achieving its 6-pillar technology innovation strategy. The company takes advantage of its distinctive presence to offer a mixture of undirected, routed, array, and spatial architectures that are used in CPUs, graphics processors, accelerators, and a programmable logic gate array – and are standardized through an open programming model that represents a standard in the sector and is represented in Interface oneAPI To simplify the application development process.

Share This Post:

Leave a Reply

Your email address will not be published. Required fields are marked *